Digital signals are received and transmitted by many types of digital electronic devices at ever increasing rates. For example, the rate at which command, address and write data signals are applied to memory devices, such as dynamic random access memory (“DRAM”) devices, continues to increase, as does the rate at which read data signals are output from memory devices. As the rate at which such signals are transmitted continues to increase, it has become more difficult to ensure that the signals are transmitted at the proper time and in synchronism with each other. For example, typical clock trees 10, 14 are shown in FIG. 1. The clock tree 10 couples a first internal clock signal ICLK1 through a series of symmetrically connected buffers 18, which may be two-transistor inverters, to the clock inputs of a plurality of latches 200, 1, . . . N. Each of the latches 200, 1, . . . N, receives at its data input a respective data bit D0, 1, . . . N, and outputs a respective data signal DQ0, 1, . . . N, to a respective DQ terminal responsive to the rising edge of the clock signal applied to the its clock input. Insofar as all of the latches 200, 1, . . . N are driven through the same clock tree 10, the DQ terminals are considered to be in the same “pin group.”
The other clock tree 14 receives a second internal clock signal ICLK2, and couples the ICLK2 signal through buffers 22 to the clock inputs of respective latches 24a,b. The data inputs of the latches 24a,b are coupled to a logic “1” level. The latch 24a therefore outputs a high data strobe signal to the DQS terminal responsive to the rising edge of the ICLK2 signal. This high at the output of the latch 24a also resets the latch 24b. The latch 24b receives the ICLK2 signal through an odd number of buffers 22 so that it outputs a high complementary data strobe signal DQS* responsive to the falling edge of the ICLK2 signal. The high at the output of the latch 24b also resets the latch 24a. The DQS and DQS* signals are considered to be in the same pin group, which is different from the DQ signal pin group.
The clock trees 10, 14 shown in FIG. 1 are typical of those used in, for example, memory controllers to output write data signals to memory devices, memory devices to output read data signals to a memory controller, or testing systems to output digital signals to devices under test. The data strobe signals DQS, DQS* are typically used in source synchronous applications to strobe data signals transmitted from the latches 20 at a receiving device. For example, in double data rate (“DDR”) memory devices, the rising edge of the DQS signal is used by a serializing device to transmit a first set of data signals from the latches 20, and the rising edge of the DQS* signal is used to transmit a second set of data signals from the latches 20. At a receiving device, the rising edge of the DQS signal is used to latch the first set of data signals from the latches 20, and the rising edge of the DQS* signal is used to latch the second set of data signals from the latches 20. In such memory devices, the DQ signals can be considered one pin group, the address signals can be considered another pin set, and the command signals can be considered still another pin set, insofar as they are each triggered by an internal clock signal coupled through different clock trees.
As the speed at which data signals are transmitted continues to increase, it has become more difficult to ensure that the DQ signals are all transmitted at the same time, and that the DQS and DQS* signals have the proper timing relative to the DQ signals. With further reference to FIG. 1, one problem with ensuring that the DQ signals are all transmitted at the same time results from unequal lengths in the signal path from the node to which the ICLK1 signal is applied to the clock inputs of the latches 20. The unequal path lengths can cause the ICLK1 signal to be applied to the latches 20 at different times, thereby causing the latches 20 to output the DQ signals at different times.
It can also be seen from FIG. 1 that the number of buffers 18 through which the ICLK1 signal propagates is different from the number of buffers 22 through which the ICLK2 signal propagates. This difference can cause the transitions of the DQS and DQS* signals to occur before or after the DQ signals output by the latches 20 are valid. The propagation time differences can be compensated for to some extent by adding delay in the signal path of the ICLK2 signal, such as by adding addition buffers. However, adding buffers that are to be used only for increasing delay takes up valuable space on a semiconductor die. Also, the propagation delays through the buffers 18, 22 generally can vary with process variations, supply voltage fluctuations, and temperature changes. Therefore, if the propagation delays of the ICLK1 and ICLK2 signals are equalized for one set of conditions, the propagation delays may no longer be equal for different processing runs of a device, for different supply voltages and/or for different temperatures. Alternatively, a smaller number of buffers 18 could be used in the clock tree 10, and each buffer 18 could be coupled to a larger number of latches 20. However, the buffers 18 would then be loaded to a greater extent than the loading of the buffers 22. As a result, the ICLK1 signal coupled through the heavily loaded buffers 18 would be delayed to a greater extent than the delay of the ICLK2 signal coupled through the lightly loaded buffers 22. As a result, the transitions of the DQS and DQS* signals might not occur at a time the DQ signals are valid.
While the number of buffers 22 through which the ICLK2 signal propagates is different from the number of buffers 18 through which the ICLK1 signal propagates, the number of buffers 18 through which the ICLK1 signal propagates to reach each of the latches 20 is the same for all branches of the clock tree 10. Therefore, the timing at which the ICLK1 signal reaches each of the latches 20 will theoretically be the same despite process, voltage and temperature variations. However, the lengths of the conductors through which the ICLK1 signal must propagate to reach each of the latches 20 will generally not be the same. Furthermore, it is generally not possible to compensate for these different propagation times by, for example, inserting additional buffers in the signal path because the propagation times of the buffers, but not the propagation time of conductors, will generally vary with process, voltage and temperature variations.
The manner in which the propagation delay of the buffers 18, 22 vary with, for example, temperature is shown in the graph of FIG. 2, which also shows the relatively constant conductor or wire propagation delay. As shown in FIG. 2, the total propagation delay is the sum of the buffer or other semiconductor element delay and the wire delays. The slope and magnitude of the total propagation delay curve will vary with the relative contribution of the semiconductor element delays and the wire delays. In general, the delay curve will be steeper if the semiconductor element delays are a higher percentage of the total delay, and it will be shallower if the wire delays are a higher percentage of the total delay. The variation in both the slope and magnitude of the total propagation delay depending on the absolute and relative delay of the semiconductor element delays and the wire delays makes it very difficult to control the output times of digital signals both within each pin group and between different pin groups.
There is therefore a need for a system and method for ensuring that digital signals are transmitted from electronic devices, such as memory devices, memory controllers, testing systems and the like, with precisely controlled timing.